The present invention relates to computer memory systems, and more specifically, to memory system power management.
Error-correcting code (ECC) memory is a type of computer data storage that can detect and correct the most common kinds of internal data corruption. Typically, ECC memory maintains a memory system that is immune to single-bit-errors. Data that is read from each memory location (e.g., a word) is always the same as the data that had been written to the location, even if one or more bits actually stored have been flipped to the wrong state. Dynamic random access memory (DRAM) devices often include extra memory bits and logic to exploit these extra memory bits to correct single bit errors in a memory bit word.
In contemporary memory systems, a memory controller scans systematically through locations in a DRAM to perform a scrub operation on each memory location in the DRAM. Memory scrub operations include reading from a memory location in a memory device, correcting single bit errors (if any) in the read data with an ECC, and writing the corrected data back to the same memory location. During the scrub process, an ECC decoder that is internal to the DRAM is used to detect and correct bit errors. By scrubbing each memory location on a frequent enough basis, the probability of encountering uncorrectable multiple bit errors is reduced. Though scrubbing provides benefits in terms of increased reliability, availability, and serviceability (RAS), it also requires additional logic in a memory controller to manage the read operation by inserting cycles in the scheduler queue, and it consumes additional power.
The trend of increasing memory system capacity has led to an increase in the amount of unused memory and thus, an increase in the power penalties experienced by memory systems when they scrub unused memory. One approach to decreasing the power penalties is to scrub unused memory right before allocation. This approach can result in an impact to performance as memory allocations will experiences relatively significant delays due to the allocation having to include a scrub of the memory. Another approach is to scrub unused memory at a slower rate, which may have the drawback of a decreased ability to detect a soft error rate, and thus RAS is traded for power savings.